LCD config register.
| LCD_DOUT_CYCLELEN | The output data cycles minus 1 of LCD module. |
| LCD_ALWAYS_OUT_EN | LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set. |
| LCD_DOUT_BYTE_SWIZZLE_MODE | 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA |
| LCD_DOUT_BYTE_SWIZZLE_ENABLE | 1: enable byte swizzle 0: disable |
| LCD_DOUT_BIT_ORDER | 1: change bit order in every byte. 0: Not change. |
| LCD_BYTE_MODE | 2: 24bit mode. 1: 16bit mode. 0: 8bit mode |
| LCD_UPDATE | 1: Update LCD registers, will be cleared by hardware. 0 : Not care. |
| LCD_BIT_ORDER | 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. |
| LCD_BYTE_ORDER | 1: invert data byte order, only valid in 2 byte mode. 0: Not change. |
| LCD_DOUT | 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. |
| LCD_DUMMY | 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. |
| LCD_CMD | 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. |
| LCD_START | LCD start sending data enable signal, valid in high level. |
| LCD_RESET | The value of command. |
| LCD_DUMMY_CYCLELEN | The dummy cycle length minus 1. |
| LCD_CMD_2_CYCLE_EN | The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. |